Variability modeling in near-threshold CMOS digital circuits

• Variability is a strong limitation for sub and near-threshold digital CMOS.
• Variability moves the minimum energy point towards the near-threshold region.
• We propose a simple model for assessing the delay-energy trade-off with variability.
• The model is validated in a 32 bit adder and a 8 bit multiplier test cases.
• We derive an analytical solution of the VDD for minimum energy with variability.

Sub-threshold operation is an efficient solution for ultra low power applications. However, it is very sensitive to process variability which can impact the robustness and effective performance of the circuit. On the other hand, this sensitivity decreases toward near-threshold operation. In this paper, the impact of variability on sub-threshold and near-threshold circuit performance is investigated through analytical modeling and circuit simulation in a 65 nm industrial low power CMOS process. It is shown that variability moves the effective minimum energy point toward the near-threshold region. Also, when variability is taken into account, a complete model including the region near-threshold (moderate inversion) is required to correctly model circuit performance around the minimum energy point. An analytical solution for the optimum supply voltage that minimizes the total energy per operation, while considering variability effects, is provided. Additionally, the resulting speed-consumption trade-off in a variability aware analysis of sub-threshold and near-threshold operation is presented.

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