A low phase noise and low spur PLL with auto frequency control circuit for L1-band GPS receiver

A low phase noise and low spur phase-locked loop (PLL) for L1-band global positioning system receiver is proposed in this paper. For obtaining low phase noise for PLL, All-PMOS LC-VCO with varactor-smoothing technique and noise-filtering technique is adopted. To reduce the reference spur, a low current-mismatch charge pump is carefully designed. A quasi-closed-loop auto frequency control circuit is used to accelerate the lock process of PLL. The PLL is fabricated in 180 nm CMOS Mixed-Signal process while it operates under 1.8 V supply voltage. The measured output frequency of PLL is 1.571 GHz and output power is −1.418 dBm. The in-band phase noise is −98.1 dBc/Hz @ 100 kHz, while the out-band phase noise is −130.3 dBc/Hz @ 1 MHz. The reference spur is −75.8 dBc at 16.368 MHz offset. When quasi closed-loop AFC is working, the measured lock time is about 10.2 μs.