An efficient triple-tail cell based PFSCL D latch

In this paper, an efficient positive feedback source-coupled logic (PFSCL) D latch topology is proposed. It uses triple-tail cell concept which results in lesser number of stages as well as gate count in comparison to the traditional PFSCL D latch. The operation of the proposed D latch is described and is supported with mathematical formulations. The functionality is verified through SPICE simulations using TSMC 0.18 µm CMOS technology parameters. It is found that the proposed D latch topology significantly reduces the power consumption and delay in comparison to the traditional PFSCL D latch. The impact of process variation on the proposed and traditional PFSCL D latch at different design corners shows similar variations.