Single-ended, robust 8T SRAM cell for low-voltage operation

Recently, an SRAM has been in the development stage, with its objective to withstand the ever-increasing process variations as well as to support ultra-low power applications, even at subthreshold supply voltages. In this paper, a new 8T SRAM cell, which employs a single bitline scheme to perform the write and read operations, is proposed. This scheme enhances the write ability and read stability by cutting off the feedback loop of the inverter pair, thereby eliminating the read and write constraints on the transistor dimensions. Additionally, it efficiently trims down the write power and standby power consumption. The experimental results show that the proposed 8T cell achieves 4.66× write ability, 2.33× read noise margin, 28.0% write power reduction, and 3.3× lower standby power dissipation when compared with a 6T bit-cell at 0.5 V through a Monte Carlo simulation (10,000 times) using the TSMC 65-nm process. Moreover, it also achieves higher process variation tolerance at an ultralow operating voltage.