A charge-pump and comparator based power-efficient pipelined ADC technique

A charge-pump and comparator based technique is presented for power-efficient pipelined analog-to-digital conversion. The technique takes advantage of a passive charge pump to implement the core function of residue voltage amplification and exploits a comparator-controlled charging circuit to buffer the residue voltage to the next stage. Unlike the conventional buffer circuit using source followers, no voltage headroom is sacrificed in this voltage buffering scheme. The comparator overshoot due to comparator delay is minimized by a self-cancellation scheme. The proposed pipelined ADC technique uses only capacitors, comparators and current sources with digital calibration to achieve low power consumption. Designed and fabricated in a 0.18 μm CMOS technology, a proof-of-concept ADC has measured 39.1 dB SNDR (6.2-bit ENOB) at 25 MS/s while consuming 3.5 mW from a 1.8 V supply.