کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
547770 872045 2010 7 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design
چکیده انگلیسی

In this paper, a new design of on-chip CMOS voltage regulator, which provides two stable power supplies to charge pump and voltage controlled oscillator (VCO) in charge pump phase-locked loop (PLL), is presented. A power supply noise rejection (PSNR) whose peaking is less than −40 dB is achieved over the entire frequency spectrum for VCO supply. The voltage regulator provides maximum 14 mA current, and static current is about 780 μA at 3.3 V. Based on the proposed voltage regulator, a PLL clock generator has been developed and measured in the AMS 0.35 μm CMOS process. Operating at 160 MHz, a period jitter of 13.64 ps was measured under a clean power supply, while period jitter became 16.24 ps under a power supply modulated with a 400 mV, 10 kHz square wave.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 41, Issue 4, April 2010, Pages 240–246
نویسندگان
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