A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs

Process-induced and environmental fluctuations play an important role in the design process for modern high-performance integrated circuits. The conventional principle of considering the verification of worst-case requirements reduces the performance that can potentially be achieved by circuits and technology. This paper presents a new mechanism that permits the compensation of random independent delay fluctuations due to environmental factors. It shows that it is significantly possible to reduce the latency time of a circuit even for a moderate length of pipeline stages.