Single Event crosstalk shielding for CMOS logic

With advances in technology scaling, CMOS circuits are increasingly more sensitive to transient pulses caused by Single Event particles. Hardening techniques for CMOS combinational logic have been developed to address the problems associated with Single Event transients, but in these designs, Single Event crosstalk effects have been ignored. In order to complement the Single Event upset (SEU) hardening process, coupling effects among interconnects need to be considered in the Single Event hardening and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. As technologies advance, the coupling effects increasingly cause SE transients to contaminate electronically unrelated circuit paths which can in turn increase the “Single Event susceptibility” of CMOS circuits. Serious effects may occur if the affected line is a clock line or an input line of voters in triple-modular redundancy (TMR) circuit. Hence, this work first analyzes Single Event crosstalk on recent technologies and then proposes hardening techniques to reduce Single Event crosstalk. Hardening results are demonstrated using HSpice Simulations with interconnect and device parameters derived in 90 nm technology.