کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
547841 872060 2009 9 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
چکیده انگلیسی

In this work, we present our experience in implementing two different cryptographic algorithms in an FPGA: IDEA and AES. Both implementations have been done by means of mixing Handel-C and VHDL and using partial and dynamic reconfiguration in order to reach a very high performance. In both cases, we have obtained very satisfactory results, achieving 27.948 Gb/s in the IDEA algorithm and 24.922 Gb/s in the AES algorithm.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 40, Issue 6, June 2009, Pages 1032–1040
نویسندگان
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