کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
547899 872070 2008 7 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Low power multipliers based on new hybrid full adders
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
Low power multipliers based on new hybrid full adders
چکیده انگلیسی

Five hybrid full adder designs are proposed for low power parallel multipliers. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates, thereby lowering the power consumption and the total number of needed transistors. For an 8×88×8 implementation, the ALL-NAND array multiplier achieves 15.7% and 7.8% reduction in power consumption and transistor count at the cost of a 6.9% increase in time delay compared to standard array multiplier. The ALL-NAND tree multiplier exhibits lower power consumption and transistor count by 12.5% and 7.3%, respectively, with a 4.4% longer time delay, compared to conventional tree multiplier.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 39, Issue 12, December 2008, Pages 1509–1515
نویسندگان
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