کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
547949 872070 2008 8 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
UDSM subthreshold leakage model for NMOS transistor stacks
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
UDSM subthreshold leakage model for NMOS transistor stacks
چکیده انگلیسی

In this paper, a new, analytical model for subthreshold leakage estimation in the ultra deep submicron (UDSM) realm is proposed. Most previous attempts at subthreshold leakage estimation in transistor stacks are not tailored for the UDSM realm and are based on either a look up table approach, and/or assume that all the transistors in the stack have a fixed width. The analytical estimation model proposed in this paper is capable of estimating subthreshold leakage in UDSM NMOS transistor stacks with different transistor widths. The model achieves this by estimating the stack nodal voltages. In this paper, transistor stacks of two, three and four transistors are considered.Compared to SPICE simulations using PTM's BSIM4 models, our analytical model achieved an average error of 8.1% for the one, two, three and four transistor stacks for 65, 45 and 32 nm CMOS process technologies. The model also exhibits significant runtime savings when compared with SPICE.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 39, Issue 12, December 2008, Pages 1809–1816
نویسندگان
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