Using metro-on-chip in physical design flow for congestion and routability improvement

Routability, signal integrity and manufacturability are important issues in physical design and congestion reduction is a widely used method for ameliorating these problems in current design methodologies. Besides, routing congestion may create large delays in detoured global wires that can be avoided by congestion reduction. In recent years, asynchronous serial transceivers are proposed for data transmission in network-on-chip systems to improve the performance of global wires. However the asynchronous transceivers have not been used for reducing the congestion and improving the routability in the physical design flow.In this paper, a new methodology is presented in which regular nets are multiplexed by asynchronous serial transceivers in the physical design flow in order to improve routing congestion and design routability. Experimental results show that for attempted benchmarks, the congestion is reduced by 18.97%, the routability is increased by 21.57% on average and total wirelength is decreased up to 9.05%. However, the overhead in power consumption and computation time are 0.12% and 10.01%, respectively, on average.