An efficient temperature dependent hot carrier injection reliability simulation flow

• Proposing an efficient temperature dependent hot carrier injection reliability simulation which is scalable.
• Proposing efficient techniques at different design levels to enable fast and high enough accurate full chip simulation.
• Suggesting to consider only the pertinent transitions which are the ones inducing the HCI impact.
• Proposing a method to classify the gates based on their impacts on the total accuracy of circuit-level HCI modeling.

This paper presents an efficient temperature dependent hot carrier injection reliability simulation flow which is scalable. The flow makes use of some efficient techniques at different design hierarchical levels to enable full chip simulation with a fast run time and high enough accuracy. While the transistor-level HCI effect is modeled based on the conventional reaction–diffusion (R–D) framework, the gate-level characterization method combines HSpice simulation and piecewise linear curve fitting to model the impact of HCI effect over the time. Also, as one of the ways to improve the speed of the simulation, only the NMOS transistors, which suffer much more from the HCI effect, are considered in the modeling. In addition, among these devices, only those which are more significantly affected are included. For each cell, only the transitions which induce the HCI impact are included. Finally, to improve the efficiency of the circuit simulation, logic cells in the circuit are classified into two groups of critical and non-critical where the critical (non-critical) ones are simulated using fine (coarse) granularity simulation time steps. The proposed method reduces the simulation time without losing much of accuracy. Also, due to the considerable impact of the temperature on the reliability, at all levels of the proposed simulation flow, the impact of the temperature on the impact of the HCI phenomena is modeled. The simulations performed on some benchmarks reveal that the proposed circuit-level HCI modeling is able to reduce the runtime of calculating the threshold voltage and mobility drifts of the gates significantly without sacrificing accuracy unacceptably. Also, the circuit-level simulations indicate an about 19% increase in the average of the HCI-induced delay degradation of the benchmarks when the temperature rises from 20 °C to 100 °C.