PVTA-aware approximate custom instruction extension technique: A cross-layer approach

Process, Voltage, and Temperature variations together with transistor Aging (PVTA) can result in significant number of timing errors in Custom Instructions (CIs) manufactured at nano-scaled silicon nodes. The state-of-the-art approach to tackle this concern is to use guard-band. However, this policy can adversely decrease the performance gain obtained by CIs as the gap between worst-case delay and true delay due to PVTA variations is increased. This paper proposes a novel approximate CI selection technique to address this issue. This technique allows the applications which do not require perfect accuracy to experience a tolerable amount of timing errors imposed by PVTA variations in favor of significantly improving the performance of the extensible processor. To achieve this, the proposed CI selection technique not only considers those CIs which their PVTA-aware delay is less than the given timing constraint, but also it takes into account the approximate CIs (i.e., those CIs that cannot strictly meet the timing constraint resulting in noisy/approximate computations). First, a timing analysis is performed to precisely compute the delay distribution of CIs in the presence of workload- and circuit-dependent PVTA variations. Then, based on the obtained distribution for each CI, a fault-map (i.e., timing error locations) is extracted. Using the fault-map, each circuit-level timing error is propagated to application-level to evaluate the quality/accuracy of the application output in the presence of PVTA-induced errors in approximate CIs. Finally, based on this cross-layer information, an optimal set of CIs is selected. This set results in maximum performance per silicon area under the given constraints on the power consumption and the errors which can be tolerated by the user. The simulations for various benchmark applications show that the proposed cross-layer technique results in up to 2.7 × speedup increase compared to the existing techniques, which comes at the expense of 6% more error.