Software verification process and methodology for the development of FPGA-based engineered safety features system

Verification process is very important for the new development or re-engineering process for Instrumentation and Control (I&C) in Nuclear Power Plant (NPP). Due to the fact that the Engineered Safety Feature-Component Control System (ESF-CCS) is safety critical system, it is necessary to specify a systematic approach to verify the performance of development design. For this verification process, a system engineering approach is used and refers to the software design life cycle to verify the VHDL code in the implementation of Field Programmable Gate Array (FPGA)-based ESF-CCS. Although FPGA does not use software, however, FPGA needs a Hardware Description Language (HDL) to describe digital and mixed-signal for an integrated system. Therefore, the VHDL code should be verified to make sure that this code level will not cause an error for the FPGA-based system, especially for ESF-CCS development. The verification method is started by looking at the requirements analysis, verification of the outputs of the design by develop software testing to verify the reliability of the code which is to support the FPGA-based ESF-CCS. White Box testing is used for software testing to demonstrate the responds from the VHDL code, whether the design is success or not, and the coverage test is at 100% coverage state. In addition, the Static Timing Analysis (STA) is applied to check the delay time. Once all verification steps have been performed, then the results of the design can be validated. In this paper, FPGA-based ESF-CCS using VHDL code is verified.