A Fully RNS based ECC Processor

This work proposes a residue number system (RNS) based hardware architecture of an elliptic curve cryptography (ECC) processor over prime field. The processor computes point multiplication in Jacobian coordinates by a combined architecture of point doubling and point addition. An optimized modular reduction architecture is also presented that achieves low area by dividing the RNS moduli in small groups and processes the groups one by one. The proposed ECC processor is generic and supports any random curve over Fp256. The implementation on Virtex-7 and Virtex-6 FPGAs shows comparable performance to the state-of-the-art binary and RNS based ECC processors.