High-performance and energy-efficient 64-bit incrementer/decrementer using Multiple-Output Monotonic CMOS

In this paper, we introduce the Multiple-Output Monotonic CMOS (M2CMOS) logic style, which is applied on the design of a high-performance and energy-efficient 64-bit incrementer/decrementer circuit. M2CMOS is proposed as an enhancement to standard monotonic-static logic and a viable alternative to domino logic for high-performance applications. A simulation-based comparative analysis at the 32 nm concludes that, compared to other state-of-the-art designs, the proposed incrementer/decrementer achieves the best results in terms of gate/transistor count, delay, energy-delay-product and standby power.