Exploring N3ASIC technology for microwave imaging architectures

When studying a new technology a critical issue is to understand its performance with respect to CMOS circuits. In this work, we analyze the performance of Nanoscale Application Specific Integrated Circuits (NASIC) and its CMOS-friendly implementation, the N3ASIC. We have created a circuit model using VHDL language. The model includes the estimation of area and power consumption of devices and blocks that can be hierarchically connected to form complex circuits. Using this model we designed a hardware accelerator for an image reconstruction algorithm for biomedical application. We synthesized the same architecture with a 45 nm-CMOS and a 7-nm FinFet library to make a comparison. The results obtained for the N3ASIC are very interesting, showing a substantial reduction in both circuit power and area.