A fast symbolic SNR computation method and its Verilog-A implementation for Sigma-Delta modulator design optimization

Sigma-Delta modulator (SDM) is a type of medium-speed but high-accuracy data converter. Signal-to-noise ratio (SNR) is one of its most critical design metrics. To enable automatic synthesis, fast SNR evaluation is of uttermost importance to accelerate the synthesis loop. In this paper a fast symbolic SNR computation method is proposed, which can automatically generate analytical SNR calculation formulas given a loop filter circuit design. Furthermore, Verilog-A implementation of this method is introduced, which demonstrates the feasibility of using the fast SNR computation method in a standard mixed-signal design automation environment. Application of the Verilog-A modules to SDM circuit optimization is demonstrated by invoking the build-in quasi-Newton optimizer in a Verilog-A tool and compared to the simulated annealing (SA) optimization. This work is an attempt of demonstration that a symbolic computation method can be integrated into a commercial mixed-signal design tool with good performance in behavioral synthesis. Utilization of the proposed method for behavioral Monte Carlo simulation in the Verilog-A environment was also found to be encouraging.