کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6942341 | 1450235 | 2015 | 10 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Power supply noise in accurate delay model for the sub-threshold domain
ترجمه فارسی عنوان
سر و صدای منبع تغذیه در مدل تاخیر دقیق برای دامنه زیر آستانه
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
چکیده انگلیسی
Ultra-Low-Power circuits demand has dramatically increased in the last few years. One of the main challenges in designing these circuits is that transistors often run in the sub-threshold regime and their on current is exponentially dependent on the gate-to-source voltage, thus making sub-threshold gates extremely susceptible to power and ground noise phenomena. This paper provides a complete mathematical model in closed form for the delay of sub-threshold CMOS inverters. The novel model can predict the behavior of inverters output signal and therefore it can be extremely useful in the design phase to analyze the variations caused by noise on the output over/undershoot and the gate delay. The proposed model has a general validity since it considers the ground and supply noises completely uncorrelated both in frequency and in amplitude. When a commercial CMOS 45Â nm process technology is referenced, the proposed model exhibits a maximum error of only ~16% under different conditions in terms of output load capacitance, input signal rising/falling time, noise phase and frequency.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 50, June 2015, Pages 127-136
Journal: Integration, the VLSI Journal - Volume 50, June 2015, Pages 127-136
نویسندگان
Pasquale Corsonello, Fabio Frustaci, Stefania Perri,