کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6944833 | 1450450 | 2018 | 10 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load
دانلود مقاله + سفارش ترجمه
دانلود مقاله ISI انگلیسی
رایگان برای ایرانیان
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
چکیده انگلیسی
A novel approach is proposed and discussed for designing CMOS double-tail dynamic comparator using the bulk-driven method. The bulk-driven method proposed thus far for low-power circuits result in reduced transconductance. The proposed technique uses the gate driven method to drive the inputs with bulk-driven loads. For the proposed comparator, mathematical analysis of delay and offset due to mismatch is presented. Additionally, a new optimized architecture of control unit is proposed to control both, offset voltage and kickback noise. To verify the outcomes, it is simulated in SPECTRE at 0.8â¯V of the supply voltage at 45â¯nm CMOS technology node. The proposed comparator achieves over 87% reduction in latch delay and 27% reduction of energy consumption over a conventional design. Monte-Carlo simulation is done to obtain the offset voltage, the result shows that the offset voltage is reduced by 62% using optimization technique.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 78, August 2018, Pages 1-10
Journal: Microelectronics Journal - Volume 78, August 2018, Pages 1-10
نویسندگان
Avaneesh K. Dubey, R.K. Nagaria,