کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6944851 | 1450450 | 2018 | 9 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
An ultra-low power multiplier using multi-valued adiabatic logic in 65â¯nm CMOS process
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: An ultra-low power multiplier using multi-valued adiabatic logic in 65â¯nm CMOS process An ultra-low power multiplier using multi-valued adiabatic logic in 65â¯nm CMOS process](/preview/png/6944851.png)
چکیده انگلیسی
The ultra-low power circuits are widely applied in energy-effective systems. This paper proposes a multi-valued adiabatic logic (MVAL) technique for energy-efficient using multiple threshold transistor and switch-level circuit. The multiple thresholds Literal Gate based on High-VTH and Low-VTH transistors are utilized to control pass-gate of adiabatic logic circuit. The presented MVAL hardware architecture can be used to energy-efficient and area reduction. Apart from the MVAL function, the proposed method supports multi-valued units with logic 0, 1, 2. The energy-effective and multi-valued adiabatic logic multiplier is implemented in 65â¯nm CMOS process. The core size of the chip occupies 0.32â¯mm2. The full-custom designed multiplier operates at alternating current (AC) power supply. It consumes 110â¯pW under 1.2â¯V supply at 300â¯MHz. Compared with other state of the art, the power dissipation decreases about 45%.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 78, August 2018, Pages 26-34
Journal: Microelectronics Journal - Volume 78, August 2018, Pages 26-34
نویسندگان
Zhang Yuejun, Ding Dailu, Pan Zhao, Wang Pengjun, Yu Qiaoyan,