Statically triggered 3×VDD-Tolerant ESD detection circuit in a 90-nm low-voltage CMOS process

A statically triggered 3 × VDD-tolerant electrostatic discharge (ESD)detection circuit using only low-voltage devices in a 90-nm 1.2-V CMOS process is proposed. A bias circuit is added to enhance the ESD trigger efficiency. Since no NMOSFETs are used, it is unnecessary to use any deep N-well even though the circuit can sustain 3 × VDD stress. The proposed detection circuit can generate a 38 mA current to turn on the substrate-triggered silicon controlled rectifier (SCR) during ESD events. Under normal operating conditions, all the devices are free from over-stress voltage. Without the gate leakage current of a MOS capacitor, the leakage current is only 63 nA under 3 × VDD stress at 25 °C. The simulation result shows the proposed circuit can be successfully used for a 3 × VDD-tolerant I/O buffer.