Novel designs for digital gates based on single electron devices to overcome the traditional limitation on speed and bit error rate

Single electron devices, SEDs, are distinguished among all new nano-scale electronic devices due to their very small size, ultra-low power consumption, and consistent technology. This paper is dedicated to digital application of single electron devices. The paper introduces a method for the speed enhancement and bit error rate reduction based on a new parallelism concept of tunneling paths and reduction of tunneling wait time. Using this method, one can go beyond the theoretical limitation of these devices in any specified technology which comes from quantum uncertainty principle. Correctness of this method is shown by analytical approaches and numerical method i.e. ensemble Monte-Carlo simulation, EMC. In this way, by proposing new designs and removal of maximum speed limitation in addition to BER reduction, this paper improves the seat of SEDs among other competing nano-scale devices.