Design and implementation of a high-throughput configurable pre-processor for MIMO detections

This paper presents the VLSI architecture and circuit implementation of a high-throughput multi-mode pre-processor for 4 × 4 MIMO detections. This design can be configured to perform pre-processing schemes including QR decomposition (QRD), Sorted QRD (SQRD), or MMSE-SQRD. Furthermore, in order to achieve high processing throughput, the proposed configurable pre-processor is architected based on the Givens rotation algorithm and a pipelined systolic array structure. Moreover, for reducing the hardware complexity and alleviating the overhead for configurability, several design innovations have been applied. Specifically, a novel norm-calculation scheme is utilized so that the overhead for the sorting operations is minimized. In addition, the utilized circuit elements are designed considering the hardware sharing paradigms. The proposed configurable pre-processor has been synthesized, placed, and routed using TSMC 90 nm technology. The post-layout estimations show that this design achieves a throughput up to 44M matrices per second for decomposing 4 × 4 channel matrix, outperforming prior works with equal functionality and architecture.