کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
6945107 1450456 2018 14 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology
چکیده انگلیسی
It is well known that high-energy particle strikes on an integrated circuit can cause circuit errors. We quantify the fraction of a layout which is susceptible to multiple transients, through the notion of critical area fraction (CAF). We perform a 2D-study on a layout of 65 nm planar transistors to evaluate maximum values of CAF. We find that CAF can be as high as 1, that is, 100% of the layout area is vulnerable. Potentials of adjacent source/drain regions play a significant role in increasing the CAF and simple layout techniques do not reduce the CAF substantially. We confirm these observations through 3D simulations of inverter layouts. A key observation is that, CAF is high in the region of the layout which contains small gates. At the circuit-level, multiple transients not only cause multiple errors, they also merge to create wider transient increasing its capture probability. A circuit-aware placement of vulnerable gates and alternate latch designs may be required to alleviate the problem.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 72, February 2018, Pages 86-99
نویسندگان
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