A fully integrated CMOS power amplifier with discrete gain control for efficiency enhancement

This paper presents the design and measurement results of a fully integrated 130 nm CMOS multimode power amplifier (PA). The proposed PA can save power consumption by performing gain reconfiguration. The circuit is composed by two stages: the first stage is responsible for setting six gain levels controlled by a 3-bit cell, while the second stage provides power amplification. The association of these two stages allows reaching a gain from 22.4 dB to 31 dB, with a power consumption ranging from 171 mW (low-gain mode) to 196.2 mW (high-gain mode), while maintaining an output power greater than 15 dBm at 2.4 GHz. The linearity of the PA when processing modulated signals is evaluated considering the requirements of IEEE802.15.4 and LTE standards. Post-layout simulation results show that the PA fully complies with IEEE 802.15.4 EVM and ACPR requirements for all 6 modes of operation for input signals up to −12 dBm and that LTE linearity requirements are partially met. Finally, digital pre-distortion is applied to the PA allowing to improve the circuit linearity for an LTE signal.