Analysis and optimal distribution scheme for SAR-VCO ADCs

A two-stage SAR-VCO ADC is typically implemented by a coarse SAR ADC (Successive Approximation Register Analog-to-Digital Convertor) and a fine voltage-controlled oscillator (VCO) based ADC. This structure is compatible with the low power and the inherent noise shaping of VCO-based ADC, which is used to quantize the residue of SAR. Based on the analysis of SAR-VCO ADC quantification procedure, this paper summarizes the impact of the stage resolution on performance of SAR-VCO ADCs by taking into consideration all interactions during the linearity, phase noise, energy dissipation and area. According to the results of behavioral modeling and simulation, the optimal resolution distribution of SAR-VCO ADC as6-bit SAR and 4-bit VCO quantization can be obtained.