کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
6945194 1450458 2017 8 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
A 10-bit 1 MS/s segmented Dual-Sampling SAR ADC with reduced switching energy
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
A 10-bit 1 MS/s segmented Dual-Sampling SAR ADC with reduced switching energy
چکیده انگلیسی
This paper implements a 10-bit segmented Dual-Sampling SAR ADC for a WPT system. To solve the mid-code problem of the Dual-Sampling structure and improve the linearity, a segmented structure is adopted in capacitive DAC. A new switching scheme is proposed for MSBs decisions to skip some of the unnecessary switching steps. This ADC is applied to digitize analog inputs of the different sub-blocks of the WPT system. Applying these techniques reduces the unit capacitor size, as well as the power consumption while improving the linearity of the system. The overall system achieves 9.8 ENOB at 1 MS/s conversion speed and consumes 19.6 μA from 3 V supply voltage. DNL and INL for this structure are measured to be −0.63-0.56 and −0.85-0.79 LSB respectively. The active area of the ADC in 0.18 μm CMOS process is 760 × 430 μm2.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 70, December 2017, Pages 89-96
نویسندگان
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