Continuos Time ΣΔ modulator with efficient gain compensated integrators

This paper presents the design of a second-order continuous time (CT) ΣΔ modulator with DC gain compensated OTA based integrators. Compared to similar solutions, this novel technique uses a simple transconductor stage to compensate for the multi-bit feedback DAC inputs in the modulator. The work details the effective compensation technique by using a negative transconductance stage that only increases a 17% of the overall ΣΔ power consumption. The compensated CT modulator is implemented in a 65 nm CMOS process and achieves a SQNR of 79.3dB and a state-of-the-art FoM of 31 fJ/conv-level.