A real-time digital calibration scheme for the cyclic ADC

A digital calibration scheme to correct the nonlinearity caused by finite amplifier gain and capacitor mismatch for the cyclic analog-to-digital converter (ADC) is presented. The calibration block of correcting the weight of the jumping points is implemented in which adders and registers are utilized without multipliers to reduce the silicon area cost. Each calibration block is shared by five ADCs. Ten switches are added into the 1.5-bit multiplying digital-to-analog converter to choose the test input signal and set the value of the most significant bit for measuring the heights of the jumping points. The capacitor mismatch and gain errors are measured as one error, and then the weight of the jumping points is compensated in the digital domain to improve the linearity of the ADC. Designed in a 0.18 μm CMOS technology, the silicon area cost of each ADC is 0.03×1.7 mm2 and the power consumption is 0.56 mW at a supply voltage of 1.8 V. The simulation results show that the calibration improves SNDR to 83.73 dB from 55.13 dB with 1% capacitance mismatch, and the calibration needs three conversion cycles which makes it real-time to obtain the changing error parameters during normal operation.