A CMOS low noise amplifier with employing noise cancellation and modified derivative superposition technique

A wide band resistive feedback CMOS low noise amplifier (LNA) with Modified Derivative Superposition (MDS) technique is designed by using TSMC RF CMOS 0.18 μm technology. In this paper, the main NMOS transistor is biased in strong inversion and auxiliary NMOS transistor is biased in the moderate inversion, so third order nonlinear current of two transistors can be canceled out and high third order input intercept point (IIP3) can be attained. In other method, the main NMOS transistor is biased in moderate inversion and an auxiliary PMOS transistor is biased in weak inversion. By this technique, second and third order input intercept point (IIP2 and IIP3) are improved. With common gate transistor in cascode structure and auxiliary transistor, thermal noise of main transistor can be canceled. The linearized LNA demonstrates IIP2 and IIP3 average improvement of +17 dB and +18 dB with PMOS transistor rather than NMOS transistor in the frequency range of 3.1-10.6 GHz. Maximum power gain of 22 dB, minimum noise figure (NF) of 2.3 dB with a power dissipation of 5.3 mW (without buffer) are obtained under a 1.8 V power supply in the frequency range of 5-10.6 GHz. The chip area is 660 µm×748 µm.