کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6945369 | 1450474 | 2016 | 12 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Ternary cyclic redundancy check by a new hardware-friendly ternary operator
ترجمه فارسی عنوان
بررسی کارآموزی سه ماهانه توسط کارآفرین سه جانبه سختافزار جدید
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
چکیده انگلیسی
This paper presents a new ternary operator for cyclic redundancy check in ternary logic with high hardware efficiency. It shows the essential properties of a ternary operator for calculating CRC. Gate-level implementation of CRC-16 is exemplified and comprehensively explained in this paper. Transistor-level realizations of the new and the previous operators are also given in full detail. This paper demonstrates that the employment of the proposed operator reduces hardware components such as the elimination of one entire operator in both transmitter and receiver sides in comparison with ternary SUM. In addition, simulation results by HSPICE and 32Â nm CNTFET technology shows about 20.6% energy reduction for one of the implementation methods of the proposed operator with respect to the previously presented one (CCW CYCLE). Furthermore, five fewer transistors are needed to design the proposed operator in contrast with both operators SUM and CCW.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 54, August 2016, Pages 126-137
Journal: Microelectronics Journal - Volume 54, August 2016, Pages 126-137
نویسندگان
Mahya Sam Daliri, Reza Faghih Mirzaee, Keivan Navi, Nader Bagherzadeh,