Fully differential charge-pump comparator-based pipelined ADC in 90Â nm CMOS

In this paper, a fully differential charge-pump comparator-based pipelined analog-to-digital converter (ADC) is presented. The fully differential capacitive gain doubler is used in the first stage as multiplying digital-to-analog converter (MDAC). Since the first stage cannot drive large capacitive loads, therefore a topology with high input impedance is chosen for the second, third and following stages. This topology does not require the common-mode feedback (CMFB) circuit. Besides, it employs the cascode current source to minimize the overshoot at the output of stages. The proposed ADC has been designed and simulated in a 90 nm CMOS technology. Simulation results show that the ADC achieves SNDR of 55.6 dB and SFDR of 64.5 dB at sampling frequency of 100 MS/s and consumes 2.8 mW from a 1 V power supply.