A variation aware timing model for a 2-input NAND gate and its use in sub-65Â nm CMOS standard cell characterization

Accurate analytical timing models are desirable for CMOS logic gates designed using nanometer technology nodes. However, many of them are available for Inverter only and other logic gates are handled by collapsing them into equivalent Inverter. Developing an accurate analytical timing model for combinational logic gates entails the challenge of inclusion of the impact of voltage transition at the intermediate nodes in the series stack of transistors. Therefore, we propose an analytical timing model for 2-input NAND gate based on the relation between the time lag between any two voltage values at the input and output nodes. While deriving our delay model we take into account the nature of voltage transition at the intermediate nodes, input-to-intermediate node capacitive coupling, parasitic capacitance at the intermediate node, and the region of operation of series connected transistors. We explore the region of validity of our derived model in the input signal transition time (TR) and load capacitance (Cl) space. To generalize our model, we relate the model coefficients with the gate size, power supply voltage (Vdd), carrier mobility, threshold voltage, and temperature. While deriving this relation, we also consider the layout dependent effects due to process induced mechanical stress. We observe that the derived models depict an average error of only 0.5% as compared to HSPICE simulation results. To demonstrate the utility of our model, we show that the use of our model reduces the number of SPICE simulations by nearly 80% of that is required for Effective Current Source Model (ECSM) library characterization. Besides this, the presented model can also be used to improve the library characterization process in Dynamic Voltage Frequency Scaling (DVFS) applications.