Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits

A new voltage mode design is presented for quaternary logic using CNTFETs. This architecture with presentation of a new structure for voltage division can be applied on any four-valued logic implementation. To ensure the functionality of this promising proposed architecture, basic gates, half-adder, and full-adder are implemented using voltage divider. Moreover, a decoder is considered to enhance the parameters of half-adder such as power consumption, delay, and number of transistors. The designs are simulated using Hspice simulation tool. In comparison with prior works, our half-adder design is optimized by 75.2%, 7.8% and 77% in power consumption, delay and PDP parameters, respectively.