AVERT: An elaborate model for simulating variable retention time in DRAMs

In DRAMs, stored data on a capacitor tend to leak over time because of leakage current. To retain data, DRAMs require periodic refresh based on a profile of retention time. However, accurate DRAM refresh characterization is hindered by variable retention time (VRT) owing to random telegraph noise. In this paper, we propose AVERT, a device model and circuit simulation methodology for variable retention time in DRAMs. Based on the charge trapping and detrapping model, we generate a random telegraph signal in trap-induced gate leakage and trap-assisted gate-induced drain leakage to model random fluctuations in the retention time of DRAMs. With AVERT, we apply a stochastic device model of variable retention time to circuit simulation. Our results demonstrate the feasibility of simulating DRAM with random telegraph noise in leakage current and correspond closely to experimental results from prior publications. Based on observations from experimental data, we provide some insight into how to optimize the test time per cell and how to reduce the overall test time of a DRAM considering VRT.