Impact of gate insulator on the dc and dynamic performance of AlGaN/GaN MIS-HEMTs

We demonstrate the following important results: (i) the gate leakage of devices with PEALD-SiN insulator is three orders of magnitude lower than that of samples with RTCVD-SiN; (ii) the use of PEALD-SiN reduces significantly the transistor threshold voltage hysteresis; (iii) both sets of samples show measurable threshold voltage shift when submitted to forward gate bias. In addition we demonstrate (iv) that the VTH shift is well correlated with the gate forward leakage and bias, for both sets of samples. This result indicates that trapping is induced by the injection of electrons in the gate insulator when a positive bias is applied to the gate; in PEALD SiN devices, the reduction of the gate (forward) leakage results in a significant decrease in VTH shift.