کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
699008 | 1460704 | 2015 | 17 صفحه PDF | دانلود رایگان |
![عکس صفحه اول مقاله: Experimental investigations on Ant Colony Optimized PI control algorithm for Shunt Active Power Filter to improve Power Quality Experimental investigations on Ant Colony Optimized PI control algorithm for Shunt Active Power Filter to improve Power Quality](/preview/png/699008.png)
• Shunt Active Power Filter (SAPF) is employed for harmonics mitigation.
• Ant colony optimized PI algorithm is proposed to enhance the performance of SAPF.
• Proposed optimal technique is compared with conventional, BF, GA and DE algorithms.
• Choice of cost function to choose the PI controller gain values is investigated.
• FPGA Implementation of the proposed algorithm.
Active Power Filters (APFs) have become a potential option in mitigating the harmonics and reactive power compensation in single-phase and three-phase AC power networks with Non-Linear Loads (NLLs). Conventionally, the assessment of gain values for Proportional plus Integral (PI) controllers used in APF employs model based controllers. The gain values obtained using traditional method may not give better results under various operating conditions. This paper presents Ant Colony Optimization (ACO) technique to optimize the gain values of PI controller used in Shunt Active Power Filter (SAPF) to improve its dynamic performance. The minimization of Integral Square Error (ISE), Integral Time Square Error (ITSE), Integral Absolute Error (IAE) and Integral Time Absolute Error (ITAE) are considered as cost functions for the proposed system. The proposed SAPF is modeled and simulated using MATLAB software with Simulink and SimPowerSystem Blockset Toolboxes. The simulation results of the SAPF using the proposed methodology demonstrates improved settling time (Ts) with ISE as cost function. For instance, the Ts for ISE 4.781 is found to be 28.5 ms. Finally, hardware implementation of the proposed SAPF system is done using Xilinx XCS500E Spartan 3E FPGA board.
Journal: Control Engineering Practice - Volume 42, September 2015, Pages 153–169