Selective growth of horizontally-oriented carbon nanotube bridges on patterned silicon wafers by electroless plating Ni catalysts

The main purpose of this research was to develop an Integrated Circuit compatible process to grow the horizontally-oriented carbon nanotubes (CNTs) across the trenches of the patterned Si wafer, which was produced by conventional photolithography technique. The selectivity of the process is based on the difference in electrical conductivity between amorphous silicon (a:Si) and silicon nitride (Si3N4), where the catalyst can be much easier deposited by electroless plating on the a:Si part of the pattern. The selectivity is also based on greater chemical reactivity of the catalyst with a:Si to form silicides, instead of with Si3N4. Furthermore, the Si3N4 barrier layer of the pattern was designed on top of the a:Si layer to guide the growth of CNTs in horizontal direction to bridge the trenches of the pattern. The as-deposited catalysts were examined by Auger electron spectroscopy (AES). The catalyst-coated pattern was pretreated in hydrogen plasma and followed by CNT growth in a microwave plasma chemical vapor deposition (MPCVD) system. The CNT bridges were characterized by scanning electron microscopy (SEM), transmission electron microscopy (TEM), high-resolution TEM (HRTEM), and I–V measurements. Under the present deposition conditions, TEM and HRTEM examinations indicate that the deposited nanostructures are bamboo-like multiwalled carbon nanotubes (MWNTs) with a wall thickness of 20∼30 graphene layers. Electrical conductivity of the as-deposited MWNTs can be greatly improved by subjecting to 760 °C heat treatment under nitrogen atmosphere. The results demonstrate that the amounts of CNTs and bridges are tunable with the Ni catalyst plating time. Under the present experimental configuration and at a catalyst plating time of 20 s, countable numbers of bridges can be obtained, which are selectively and horizontally grown on the areas of the pattern with Ni catalyst. This process can be a step approaching the application of CNTs in electronic devices.