An efficient automated topology processor for state estimation of power transmission networks

A robust network topology processor that can be utilized in both traditional and PMU-based state estimators is developed. Previous works in the field of topology processing are scrutinized and their drawbacks are identified. Building on top of the state of the art, an algorithm covering the limitations of available topology processing approaches and including new features is proposed. The presented algorithm was implemented in MATLAB and tested using two different power networks with detailed substation configurations (bus/breaker models) including a modified version of the IEEE Reliability Test System 1996. As the topology processor is intended to supply network topologies to a PMU-based Sate Estimator, the IEEE Reliability Test System 1996 is simulated in real-time using the eMegaSim Opal-RT real-time simulator which is part of “SmarTS Lab” at KTH Royal Institute of Technology. Testing is carried out through several test scenarios and computation times are calculated. It is shown that the computation times are adequate for supporting a PMU-only state estimator.