Optimum structure of a generalized three-phase reduced switch multilevel inverter

This study presents a new generalized three-phase multilevel converter based on the combinations of half-bridge modules along with a three-phase T-Type multilevel inverter. The proposed topology reduces the number of switches and associated gate-driver circuits that attains much higher number of output voltage levels. The optimized structure of the proposed three-phase inverter topology has been developed to obtain the maximum number of output voltage levels of the inverter with a minimum number of power electronic switches and the DC voltage sources. The operation, control and performance analysis of the proposed generalized multilevel inverter have been considered here. A nearest level control (NLC) technique is adopted to generate the gating signal for the proposed three-phase hybrid inverter. A laboratory prototype of a specimen three-phase low power fifteen-level inverter have been designed using twenty four switches and nine voltage sources. The conduction losses of the proposed fifteen level inverter is around 14.71 watt/phase compared to 23.26 watt/phase in an asymmetrical cascaded inverter. The exhaustive simulations of the proposed three-phase inverter are performed using MATLAB/SIMULINK and the results are verified experimentally and presented for the different modulation index.