Enhanced Architecture of FIR Filters Using Block Memories

The paper presents an enhanced architecture of finite impulse response digital filters. The proposed architecture contains one multiply-accumulate unit and random access memory to store data. The architecture utilizes serial calculation to achieve minimum requirements on area. The architecture is suitable for implementation in application specific integrated circuits and field programmable gate arrays. The main advantages of the architecture are higher operating frequency, lower power consumption and smaller area utilization in particular cases.