کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
719071 1461218 2016 8 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Low-cost FPGA implementation of 2D digital pre-distorter for concurrent dual-band power amplifier
موضوعات مرتبط
مهندسی و علوم پایه سایر رشته های مهندسی مهندسی برق و الکترونیک
پیش نمایش صفحه اول مقاله
Low-cost FPGA implementation of 2D digital pre-distorter for concurrent dual-band power amplifier
چکیده انگلیسی

This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter (DPD). The architecture is implemented on field programmable gate array (FPGA) to compensate for the nonlinearity of the concurrent dual-band power amplifier (PA). This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables (LUTs) sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio (ACPR) is less than 59 dBc and normalized mean square error (NMSE) is around 62dB for lower sideband (LSB) and 63dB for upper sideband (USB).

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: The Journal of China Universities of Posts and Telecommunications - Volume 23, Issue 1, February 2016, Pages 14-21