A performance optimized architecture of deblocking filter for H.264/AVC

The in-loop deblocking filter is one of the complex parts in H.264/AVC. It has such a large amount of computation that almost all the pixels in all the frames are involved in the worst case. In this paper, a fast deblocking filter architecture is proposed, and it can effectively save the operating time. In the proposed architecture, two 1-D filters are introduced so that the vertical filtering and the horizontal filtering can be performed at the same time, Only 120 cycles are needed for a macroblock. Our architecture is also a memory efficient one, and only one 4x4 pixels register, one 4x4 transpose array and one 16x32 b two-port (SRAM) are used as buffers in the filtering process. The simulation and synthesis results show that, with almost the same or even smaller area than some 1-D filter based architectures before, the proposed one can save more than 40% processing time. The architecture is suitable for real-time applications and can easily achieve the requirement of processing real-time video in 1080HD (high definition format, 1 920x1 088@30 fps) at 100 MHz.