A fault tolerant architecture to avoid the effects of Single Event Upset (SEU) in avionics applications

• Radiation effects on FPGA-based avionics devices are discussed.
• A fault tolerant architecture to avoid the radiation effects is proposed.
• A reliability model to validate the architecture has been developed.

Commercial-Off-The-Shelf (COTS) Field Programmable Gate Array (FPGA) is becoming of increase interest in many field of high-tech applications for the possibility to implement low-cost solutions with simplicity and flexibility. Nevertheless, the presence of high energy incident particles (electrons, neutrons, protons and so on) can compromise the functionality of these devices when they are used in particular environmental conditions. This is the case of avionics and space environment, where high reliability levels are necessary as project requirements and the occurrence of a fault condition, or a disturbance, cannot be ignored. To this aim the paper focuses the attention on the fault tolerant techniques for FPGA-based avionics devices in presence of radiation disturbances induced by incident particles. After a brief description of the radiation phenomenon and the effects induced on the electronic device, an evaluation of the Single Event Upset (SEU) with relative effects is carried out. Then a new fault tolerant approach is proposed in the paper in order to determine a diagnostic and correction technique. To achieve the requirements of a complex avionics system, an Integrated Control Panel for military aircraft cockpit is taken into account on this system. Several specific tests have been also carried out in order to simulate upset conditions and to prove the validity of the proposed technique.