Hardware design and implementation of a novel ANN-based chaotic generator in FPGA

This paper presents a novel hardware implementation of Artificial Neural Networks (ANNs) for modeling of the Pehlivan–Uyaroglu Chaotic System (PUCS) on Field Programmable Gate Array (FPGA). There are two main parts in the proposed work. In the first part, a 3-8-3 Feed Forward Neural Network (FFNN) has been created using Matlab R2015a. The training results show that FFNN trained with back propagation algorithm exhibits satisfactory precision for the direct implementation. In the second part, the hardware implementation of the trained network has been carried out. The designed architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL) and is implemented on a Xilinx Virtex 6 (XC6VCX240T) chip. All related parameters are defined with IEEE 754 single precision floating point number format. For the approximation of Log-Sigmoid transfer function, Xilinx's COordinate Rotation DIgital Computer (CORDIC) design has been employed. The design can be used with a clock frequency up to 266.429 MHz. Finally, chip statistics of FPGA and analysis results have been presented. The proposed work have showed that chaotic systems can be successfully modeled using ANNs on FPGA. In future, chaos-based engineering applications can be performed using ANN-based chaotic oscillators on FPGA.