Tiles chamfering and power handling of the MK II HD divertor

The JET high triangularity (δ, HD) divertor is an upgrade of the present JET divertor consisting of two modified toroidal segments which are: a new load bearing septum replacement plate (LB-SRP) tile located in the center of the divertor and a high field gap closure (HFGC) tile protecting inboard diagnostic cabling. The aim of the upgrade is to allow high power operation and a wider range of plasma triangularities at the divertor poloidal null. This paper describes the optimisation of the tile chamfering (including edge shadowing) and the power handling evaluation for a set of 12 planned plasma configurations given by the JET team and on two sets of mechanical tile tolerances issued by the JET drawing office. The PROTEUS code (magnetic equilibrium by finite element) is used to calculate the various field line angles, which are inputs for the chamfering angle calculation process. After calculating the chamfering angle values of each face, a checking exercise has been realised on the 3D CATIA models of the tiles by putting them at their extreme tolerance positions and validating if the shadowing is ensured for a angle calculated to take into account the worst possibilities. With the final chamfering angle value for each face, the power handling of the tiles has been estimated with finite element calculations. Power handling is given either by the critical time to reach 1800 °C at the tile surface for a total injected power of 40 MW or by the maximum total injected power allowable for a 10 s power pulse without exceeding 1800 °C. The estimated power handling gives promising results in regard to the JET EP project objectives.