Gate stress effect on low temperature data retention characteristics of split-gate flash memories

In modeling post-cycling low temperature data retention (LTDR) characteristics of split-gate flash memories, gate stress is used to accelerate the charge gain effect responsible for bit cell current reduction among tail bits. To determine the adequate stress condition, various gate stress voltages are performed to enhance the charge gain effect of the flash memory cells. In addition, by analyzing the leakage mechanism and the data retention behavior of cells under gate stress conditions, reliability tests can be completed in a much shorter period and still provide accurate lifetime prediction for embedded memory products.