کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
9672147 1450564 2005 6 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Negative bias temperature instability mechanisms in p-channel power VDMOSFETs
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
Negative bias temperature instability mechanisms in p-channel power VDMOSFETs
چکیده انگلیسی
The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge. The results are analysed in terms of the mechanisms responsible for buildup of oxide charge and interface traps, and the model that explains experimental data is discussed in details.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Reliability - Volume 45, Issues 9–11, September–November 2005, Pages 1343-1348
نویسندگان
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